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HSDL-3201
IrDA(R) Data 1.4 Low Power Compliant 115.2 kb/s Infrared Transceiver
Data Sheet
Features
Ultra small surface mount package Minimal height: 2.5 mm VCC from 2.7 to 3.6 volts Withstands > 100 mVp-p power supply ripple LED supply voltage can range from 2.7 to 6.0 volts * Low shutdown current - 20 nA typical * Lead-free and RoHS compliant * * * * * * Complete shutdown - TxD, RxD, PIN diode * One optional external component * Temperature range: -25C to 85C * 32 mA LED drive current * Integrated EMI shield * IEC825-1 Class 1 eye safe * Edge detection input - Prevents the LED from long turn on time
CELL PHONES PAGERS PDAs CAMERAS
.4 IrDA 1 R OWE LOW P
30
ILL
UM
IN
A
N TIO
CO
NE
.0/1.4 IrDA 1 D OR NDAR R STA OWE LOW P
CELL PHONES PAGERS PRINTERS 20 CM TO LOW POWER DEVICES 30 CM TO STANDARD DEVICES PCs PDAs CAMERAS
Applications
* Mobile telecom - Cellular phones - Pagers - Smart phones * Data communication - PDAs - Portable printers * Digital imaging - Digital cameras - Photo-imaging printers
Application Circuit
8 VLED
LED CURRENT SOURCE
VLED
TXD
7 TXD
RXD SHUT DOWN
6 RXD 5 SD
SHIELD
4 AGND
Description
The HSDL-3201 is one of a new generation of low-cost Infrared (IR) transceiver modules from Avago Technologies. It features the smallest footprint in the industry at 2.5 H x 8.0 W x 3.0 D mm. Although the supply voltage can range from 2.7 V to 3.6 V, the LED drive current is internally compensated to a constant 32 mA to assure that link distances meet the IrDA Data 1.4 (low power) physical layer specifications. The HSDL-3201 meets the 20 cm link distance to other IrDA 1.4 low power devices, and a 30 cm link distance to IrDA 1.4 standard devices.
VCC C1 1.0 F
3 2
VCC NC
RX PULSE SHAPER
1 GND
I/O Pins Configuration Table
Pin 1 2 3 4 5 6 7 Symbol GND NC VCC AGND SD RXD TXD Description Ground No Connection Supply Voltage Analog Ground Shut Down Active High Receiver Data Output. Active Low. Transmitter Data Input. Active High. Notes Connect to system ground. This pin must be left unconnected. Regulated: 2.7 to 3.6 Volts Connect to a "quiet" ground. This pin must be driven either high or low. Do NOT float the pin. Output is a low pulse for 2.4 s when a light pulse is seen. Logic high turns the LED on. If held high longer than ~ 20 s, the LED is turned off. TXD must be driven high or low. Do NOT float the pin. May be unregulated: 2.7 to 6.0 volts. Connect to system ground via a low inductance trace. For best performance, do not directly connect to GND or AGND at the part.
HSDL-3201#021 Pinout, Rear View
8 VLED SHIELD LED Voltage EMI Shield
8
7
6
5
4
3
2
1
HSDL-3201#008 Pinout, Rear View
8
7
6
5
4
3
2
1
2
Recommended Application Circuit Components
Component C1 Recommended Value 1.0 F Note 1
Shutdown Mode Notes
When the HSDL-3201 is in Shutdown Mode (SD pin high), the part presents different impedances to the rest of the circuit than when it is in normal mode. RXD Pin: This pin is NOT Tri-state. During shutdown the equivalent circuit is a weak pullup (~300 k) to VCC. The ESD protection diodes to VCC and Ground are also present. TXD Pin: Input protection diodes are present. VLED Pin: Possible leakage current of 1.5 nA. SD Pin: Will draw approximately 16 nA when driven high.
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is 50C/W. Parameter Storage Temperature Operating Temperature LED Supply Voltage Supply Voltage Input Voltage: TXD, SD Output Voltage: RXD Solder Reflow Temperature Profile Symbol TS TA VVLED VCC VI VO Min. Max. -40 100 -25 85 -0.5 67 -0.5 7 6 0 6VCC + 0.5 -0.5 6VCC + 0.5 See Reflow Profile, page 19 Units C C V V V V
Transceiver I/O Truth Table
The LED and RXD outputs are controlled by the combination of the TXD and SD pins and light falling on the receiver. As shown in the table below, the transmitter is noninverting; the LED is on when the TXD pin is high and off when TXD is low.
The receiver is inverting; the RXD pin is low during IrDA signal pulses and high when the receiver does not see any light. When shutdown (SD pin high), the LED is off (the state of the TXD pin does not matter), and the RXD pin is pulled high with a weak internal pullup.
Marking Information
The unit is marked with the letter "A" and "YWWLL" on the shield for front options where Y is the last digit of the year, WW is the workweek, and LL is the lot information. For top options, the part is marked as "YWW" where Y is the last digit of the year, and WW is the workweek.
SD Low High
TXD High Low Don't care
LED On Off Off
Receiver Don't care IrDA Signal No Signal Don't care
RXD Not Valid Low High High
Notes 2, 3 4, 5 6
Ordering Information
Specify the part number followed by an option number. HSDL-3201#XXX There are two options available: Front Options #021 Taped and 13" Reel Packaging, 2500 per reel Top Options #008 Taped and 13" Reel Packaging, 2500 per reel
Caution: The BiCMOS inherent to this design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
3
Recommended Operating Conditions Parameter Symbol Operating Temperature TA Supply Voltage VCC LED Supply Voltage VLED TXD, SD Input Logic High VIH Voltage Logic Low VIL Receiver Input Logic High EIH Irradiance Logic Low EIL Receiver Data Rate
Min. -25 2.7 2.7 VCC-0.5 2/3 VCC 0 0.0081 2.4 9.6
Max. 85 3.6 5 6.0 VCC VGND+0.4 1/3 VCC 500 0.3 115.2
Units
C
Conditions
Notes
V V V V mW/cm2 W/cm2 kb/s
For in-band signals. For in-band signals.
7 7
RXD Output Waveform
tpw VOH 90% 50% 10%
Receiver Wakeup Time Definition
SD
RX LIGHT
VOL
RXD
tf
tr
tRW
LED Optical Waveform
tpw LED ON 90% 50% 10% LED OFF
Transmitter Wakeup Time Definition
SD
TXD
tr
tf
TX LIGHT tTW
TXD "Stuck ON" Protection
TXD
LED
tpw (MAX.)
4
Electrical & Optical Specifications
Specifications hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values are at 25C and 3.0 V unless otherwise noted. Parameter Receiver Viewing Angle Peak Sensitivity Wavelength RXD Output Logic High Voltage Logic Low RXD Pulse Width RXD Rise Time RXD Fall Time Receiver Latency Time Receiver Wake Up Time Transmitter Radiant Intensity Viewing Angle Peak Wavelength Spectral Line Half Width Optical Pulse Width Max. Optical Pulse Width Optical Rise Time Optical Fall Time TXD Logic High Levels Low TXD Input High Current Low LED On Current Off Shutdown Transmitter Wake Up Time Transceiver SD Logic High Levels Low SD Input High Current Low DC Supply Shutdown Current Idle AC Supply Active, Current Receive Active, Transmit
Notes at top of next page.
Symbol 2f1/2 lp VOH VOL tPW tR tF tL tRW EIH 2q1/2 lp Dl1/2 tOPW tOPWM tOR tOF VIH VIL IH IL IVLED IVLED IVLED tTW VIH VIL IH IL ICC1 ICC2 ICC3 ICC4
Min. 30
Typ.
Max.
Units nm
Conditions
Note
880 VCC -0.2 0 2.0 2.45 50 50 11 30 16 50 25 28 200 4 30 9 875 35 1.6 20 180 180 VCC 0.4 3.0 120 20 80 25 100 50 40 500 28.8 60
V V s ns ns s s
IOH=-200 A, EI 0.3 W/cm2 IOL=200 A tPW (EI)=1.6 s, CL =10 pF tPW (EI)=1.6 s, CL =10 pF
8 8
9 10 TA = 25C, q1/2 15, TXD 2/3 VCC VCC-0.5
1.41
2/3 VCC VCC-0.5 0 25 -15 35 32 1.5 1.5 12 2/3 VCC VCC-0.5 0
mW/Sr nm nm 2.23 s 30 s 600 ns 600 ns VCC V VGND+0.4 V 1/3 VCC nA nA mA nA nA 20 s
tPW (TXD) = 1.6 s TXD pin stuck high tPW (TXD) = 1.6 s tPW (TXD) = 1.6 s
VCC-0.5 VI 2/3 VCC VGND+0.4 0 VI 1/3 VCC VCC-0.5 VVLED=VCC=3.6 V, VI(TXD) 2/3 VCC VGND+0.4 VVLED=VCC=3.6 V, VI(TXD) 1/3 VCC VI(SD) 2/3 VCC VCC-0.5
11
VCC V 1/3 VCC VGND+0.4 V 16 nA 10 -150 nA 20 200 nA 100 A 0.8 3.0 mA 9.0 mA
VCC-0.5 VI 2/3 VCC 0 VI 1/3 VCC VGND+0.4 VCC=3.6 V,VSD VCC - 0.5, TA=25C VGND+0.4,EI=0 VCC=3.6 V, VI(TXD) 1/3 VCC, EI=0 VCC=3.6 V, VI(TXD) 1/3 VCC VGND+0.4
12,13 14
VCC=3.6 V, VI(TXD) 2/3 VCC VCC-0.5
5
Notes: 1. C1 must be placed within 0.7 cm of the HSDL-3201 to obtain optimum noise immunity. 2. If TXD is stuck in the high state, the LED will turn off after about 20 s. 3. RXD will echo the TXD signal while TXD is transmitting data. 4. In-Band IrDA signals and data rates 115.2 Kb/s. 5. RXD Logic Low is a pulsed response. The pulse width is 2.4 s, independent of data rate. 6. RXD Logic High during shutdown is a weak pullup resistor (300 k). 7. An in-band optical signal is a pulse/sequence where the peak wavelength, lp, is defined as 850 nm lp 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification. 8. For in band signals 115.2 Kb/s where 8.1 W/cm2 EI 500 mW/cm2. 9. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered full sensitivity. 10. Receiver wake up time is measured from the SD pin high to low transition or VCC power on, to a valid RXD output. 11. Transmitter wake up time is measured from the SD pin high to low transition or VCC power on, to a valid light output in response to a TXD pulse. 12. Typical values are at EI = 10 mW/cm2 13. Maximum value is at EI = 500 mW/cm2. 14. Current is due to internal stages of the LED current mirror. This current is in addition to the ILED current.
Notes on Supply Current The supply current for the HSDL-3201 has two different components, DC and AC. The DC component is measured in two states, normal (idle mode) and shutdown. This current is present whenever power is applied to the part. The AC component is either the extra current drawn from the VCC pin by the photodiode when it sees light, or the current needed by the LED current circuit. The values in the table are peak values. Since IrDA data is transmitted with a 3/16 duty cycle, the average value is 3/16 of the peak. The AC current is not drawn when no light is present.
Distances between Units to See a 10 mW/cm2 Light Level
Type of Transceiver Typical HSDL-3201 Max. Brightness HSDL-3201 Typical SIR Typical FIR Distance (cm) 1.0 1.7 2.0 3.2
The 500 mW/cm2 light level is for the maximum brightness IrDA unit at 1 cm.
34.0 VLED = 3.6 VOLTS 33.5 33.0
ILED - mA
34.0 33.5 33.0
ILED - mA
VCC = 3.6 VOLTS VCC = 3.3 VOLTS
32.5 32.0 31.5 31.0 Figure 1. LED current vs. VCC. 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC - VOLTS
32.5 32.0 31.5
VCC = 3.0 VOLTS
VCC = 2.7 VOLTS
31.0 Figure 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 2. LED current vs. VLED. VLED - VOLTS
Figure 1. LED current vs. VCC.
Figure 2. LED current vs. VLED.
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HSDL-3201#021 Package Dimensions
MOUNTING CENTER
4.0 1.025
2.05 RECEIVER
C L EMITTER 2.2 1.175
2.5
2.85
1.05 1.25 2.55 4.0
0.35 0.65 0.80
;;;; ;
8.0 3.0 1.85
2.9
PIN1
C L
UNIT: mm TOLERANCE: 0.2 mm COPLANARITY = 0.1 mm MAX.
0.6 6.65
PIN 1 3.325
7
HSDL-3201#021 Tape and Reel Dimensions
UNIT: mm
4.0 0.1 + 0.1 1.5 0 1.75 0.1 1.5 0.1
POLARITY PIN 8: VLED 8.4 0.1 PIN 1: GND 3.4 0.1 0.4 0.05 2.8 0.1 PROGRESSIVE DIRECTION 8.0 0.1 7.5 0.1 16.0 0.2
EMPTY (40 mm MIN.)
PARTS MOUNTED
LEADER (400 mm MIN.) EMPTY (40 mm MIN.)
OPTION # "B" "C" QUANTITY 001 021 UNIT: mm 178 330 60 80 500 2500
DETAIL A 2.0 0.5 13.0 0.5 B C
R 1.0 LABEL 21 0.8 DETAIL A 2 16.4 + 0 2.0 0.5
8
HSDL-3201#008 Package Dimensions
3.6 2 1.55 C L 1.55 2
+0.05 2.8 -0.2 +0.05 1.8 -0.2 C L
PIN1
2.8 3.35 2.35 0.4 0.15
0.7 0.1
;; ;;;;
7.5
5.1
0.6 0.15 0 0.05 (MAX.) 3.325 0.95 x 7 = 6.65 0.15
0.95 0.1
0.3
UNIT: mm TOLERANCE: 0.2 mm COPLANARITY = 0.1 mm MAX.
PIN1
Pin 1 2 3 4 5 6 7 8 9
Symbol GND NC VCC AGND SD RxD TxD VLED EMI Shield
Description Ground No Connection Supply Voltage Analog Ground Shutdown (Active High) Receive Data Transmit Data LED Voltage EMI Shield
9
HSDL-3201#008 Tape and Reel Dimensions
60TYP.
99.5 1 120 3 +0.5 13.1 -0
264 PS 330 1 1 2 DETAIL A (5/1)
+0.5 16.0 -0
D1
Po
P2
Do
B
E
F
;;;
A A Ao 5(MAX.) 5 3.1 0.1 A-A SECTION UNIT: mm SYMBOL SPEC SYMBOL SPEC Ao 3.65 0.10 E 1.75 0.10
P1
B
;; ;; ;;
T 5(MAX.) 2.6 W Bo 5 1.5 Ko T 0.40 0.10
B-B SECTION
Bo 7.90 0.10 F 7.50 0.10
Ko +0.05 2.75 - 0.10 Do 1.55 0.05
Po 4.00 0.10 D1 1.50 (MIN.)
P1 8.00 0.10 W
P2 2.00 0.10 10Po
16.00 0.30 40.00 0.20
NOTES: 1. 10 SPROKET HOLE PITCH CUMULATIVE TOLERANCE IS 0.2 mm. 2. CARRIER CAMBER SHALL NOT BE MORE THAN 1 mm PER 100 mm THROUGH A LENGTH OF 250 mm. 3. Ao AND Bo MEASURED ON A PLACE 0.3 mm ABOVE THE BOTTOM OF THE PACKET. 4. Ko MEASURED FROM A PLACE ON THE INSIDE BOTTOM OF THE POCKET TO TOP SURFACE OF CARRIER. 5. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED AS TRUE POSITION OF POCKET, NOT POCKET HOLE.
10
Moisture Proof Packaging
The HDSL-3201 is shipped in moisture proof packaging. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 4. 3.
Recommended Land Pattern for HSDL-3201#021 (Front Options)
C L 1.35 SHIELD SOLDER PAD MOUNTING CENTER
1.25
2.05
Recommended Storage Conditions
Storage Temperature Relative Humidity 10C to 30C
0.10
0.775
below 60% RH
1.75
Time from Unsealing to Soldering
After removal from the bag, the parts should be soldered within three days 7 if stored at the recommended storage conditions.
FIDUCIAL 0.60 0.475 1.425 UNIT: mm 2.375 3.325
Baking
If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Package In reels In bulk Temp. 60C 100C 125C 150C Time 48 hours 4 hours 2 hours 1 hour
Baking should only be done once.
;;;; ;; ;;;;; ;;;;;; ;;;; ;;;; ;;
2.20 1.45 0.9 1.275 MOUNTING CENTER 1.60 0.60 PITCH 7 x 0.95 3.625
Recommended Land Pattern for HSDL-3201#008 (Top Options)
0.575
11
Appendix A: HSDL-3201#021 SMT Assembly Application Note Solder Pad, Mask, and Metal Stencil
METAL STENCIL FOR SOLDER PASTE PRINTING
STENCIL APERTURE
LAND PATTERN
SOLDER MASK PCB
Recommended Metal Solder Stencil Aperture
It is recommended that only a 0.127 mm (0.005 inches) or a 0.11 mm (0.004 inches) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern.
APERTURES AS PER LAND DIMENSIONS
t
w l
Stencil Thickness, t (mm) 0.127 mm 0.11 mm
Aperture Size (mm) length, l width, w 1.75 0.05 0.55 0.05 2.4 0.05 0.55 0.05
12
Adjacent Land Keep-Out and Solder Mask Areas
Adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. It is recommended that two fiducial crosses be place at mid-length of the pads for unit alignment. Note: Wet/Liquid Photo-Imageable solder resist/mask is recommended.
8.2
0.2 2.6
SOLDER MASK UNITS: mm
3.0
13
PCB Layout Suggestion
The following PCB layout shows a recommended layout that should result in good electrical and EMI performance. Things to note: 1. The ground plane should be continuous under the part, but should not extend under the shield trace. 2. The shield trace is a wide, low inductance trace back to the system ground. 3. The AGND pin is connected to the ground plane and not to the shield tab.
Component Side
C1
SHUTDOWN
GROUND
5. VLED can be connected to either unfiltered or unregulated power. If C1 is used, and if V LED is connected to VCC, the connection should be before the C1 cap.
Circuit Side
14
SHIELD
4. C1 is an optional VCC filter capacitor; it may be left out if the Vcc is clean.
VLED
TXD
RXD
VCC
Recommended Solder Paste/Cream Volume for Castellation Joints
Based on calculation and experi-ment, the printed solder paste volume required per castellation pad is 0.22 cubic mm (based on either no-clean or aqueous solder cream types with typically 60% to 65% solid content by volume). Using the recommended stencil results in this volume of solder paste.
Direction Definition
Tolerance for X-axis Alignment of Castellation Misalignment of castellation to the land pad should not exceed 0.2 mm or about one half the width of the castellation during placement of the unit. The castellations will self-align to the pads during solder reflow. Tolerance for Rotational (q) Misalignment Mounted units should not be rotated more than 3 degrees with reference to center X-Y as shown in the direction definition. Units that are rotated more than 3 degrees will not self align after solder reflow. Units with less than a 3 degree misalign-ment will selfalign after solder reflow.
Y-axis Misalignment of Castellation In the Y direction, the HSDL-3201 does not self align after solder reflow. Avago recommends that the part be placed in line with the fiducial mark (midlength of land pad.) This will enable sufficient land length (minimum of one half of the land pad) to form a good joint. See the drawing below.
Pick and Place Misalignment Tolerance and Self-Alignment after Solder Reflow
If the printed solder paste volume is adequate, the HSDL-3201 will self align after solder reflow. Units should be properly reflowed in IR/Hot Air convection oven using the recommended reflow profile. The direction of board travel does not matter.
EDGE
Y X
MINIMUM 1/2 THE LENGTH OF THE LAND PAD FIDUCIAL
Allowable Misalignment
Direction X Y q Tolerance 0.2 mm See text 3 degrees
15
Recommended Reflow Profile
255 MAX. 260C
R3 R4
T - TEMPERATURE - (C)
230 220 200 180 160 120 80 25 0 P1 HEAT UP 50 100 150 200 P3 SOLDER REFLOW 250 P4 COOL DOWN 300 R1 R2 60 sec. MAX. ABOVE 220C
R5
t-TIME (SECONDS) P2 SOLDER PASTE DRY
Process Zone Heat Up Solder Paste Dry Solder Reflow Cool Down
Symbol P1, R1 P2, R2 P3, R3 P3, R4 P4, R5
DT 25C to 160C 160C to 200C 200C to 255C (260C at 10 seconds max.) 255C to 200C 200C to 25C
Maximum DT/Dtime 4C/s 0.5C/s 4C/s -6C/s -6C/s
The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates. The DT/ Dtime rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3201 castellation I/O pins are heated to a temperature of 160C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4C per second to allow for even heating of both the PC board and HSDL-3201 castellation I/O pins.
Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200C (392F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255C (491F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth
within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200C (392F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25C (77F) should not exceed 6C per second maximum. This limitation is necessary to allow the PC board and HSDL-3201 castellation I/O pins to change dimensions evenly, putting minimal stresses on the HSDL-3201 transceiver.
16
WINDOW HEIGHT Y - mm
;; ; ;;;; ;;;;
Z X
Window Design To insure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30 degrees, the maximum, to a cone angle of 60 degrees.
Minimum and Maximum Window Sizes
Dimensions are in mm. Depth (Z) 0 1 2 3 4 5 6 7 8 9 10 Y min. 1.70 2.23 2.77 3.31 3.84 4.38 4.91 5.45 5.99 6.52 7.06 X min. 6.80 7.33 7.87 8.41 8.94 9.48 10.01 10.55 11.09 11.62 12.16 Y max. 3.66 4.82 5.97 7.12 8.28 9.43 10.59 11.74 12.90 14.05 15.21 X max. 8.76 9.92 11.07 12.22 13.38 14.53 15.69 16.84 18.00 19.15 20.31
Window Height Y vs. Module Depth Z
Y
16 60 CONE 14 12 10 8 6 4 2 0 0 2 4 6 8 10 ACCEPTABLE RANGE 30 CONE
X is the width of the window, Y is the height of the window, and Z is the distance from the HSDL-3201 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens is 5.1 mm. The equations for the size of the window are as follows: X = 5.1 +2(Z + D) tan q Y = 2(Z + D) tan q Where q is the required half angle for viewing. For the IrDA minimum, it is 15 degrees, for the IrDA maximum it is 30 degrees. (D is the depth of the LED image inside the part, 3.17 mm). These equations result in the following tables and graphs:
MODULE DEPTH Z - mm
Window Width X vs. Module Depth Z
22 20
WINDOW WIDTH X - mm
60 CONE
18 16 14 12 10 8 6 0 2 4 6 8 10 ACCEPTABLE RANGE
30 CONE
MODULE DEPTH Z - mm
17
Shape of the Window From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical design reasons, place a curve on the back side of the window that has the same radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will reduce the effects. The amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm.
Flat Window (First choice)
Curved Front and Back (Second choice)
Curved Front, Flat Back (Do not use)
18
Test Methods
Background Light and Electromagnetic Field There are four ambient interference conditions in which the receiver is to operate correctly. The conditions are to be applied separately: 1. Electromagnetic field: 3 V/m maximum (please refer to IEC 801-3, severity level 3 for details). 2. Sunlight: 10 kilolux maximum at the optical port. This is simulated with an IR source having a peak wavelength within the range of 850 nm to 900 nm and a spectral width of less than 50 nm biased to provide 490 W/cm2 (with no modulation) at the optical port. The light source faces the optical port. This simulates sunlight within the IrDA spectral range. The effect of longer wavelength radiation is covered by the incandescent condition.
3. Incandescent Lighting: 1000 lux maximum. This is produced with general service, tungsten-filament, gas-filled, inside frosted lamps in the 60 Watt to 100 Watt range to generate 1000 lux over the horizontal surface on which the equip-ment under test rests. The light sources are above the test area. The source is expected to have a filament temperature in the 2700 to 3050 Kelvin range and a spectral peak in the 850 to 1050 nm range. 4. Fluorescent Lighting: 1000 lux maximum. This is simulated with an IR source having a peak wavelength within the range of 850 nm to 900 nm and a spectral width of less than 50 nm biased and modulated to provide an optical square wave signal (0 W/cm 2 minimum and 0.3 W/cm2 peak amplitude with 10% to 90% rise and fall times less than or equal to 100 ns) over the horizontal surface on which the equipment under test rests. The
light sources are above the test area. The frequency of the optical signal is swept over the frequency range from 20 kHz to 200 kHz. Due to the variety of fluorescent lamps and the range of IR emissions, this condition is not expected to cover all circumstances. It will provide a common floor for IrDA operation.
19
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http://optodatabook.liteon.com/databook/databook.aspx
Data subject to change. Copyright (c) 2007 Lite-On Technology Corporation. All rights reserved.

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